 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| EM620FV16B Series Low Power, 128Kx16 SRAM Document Title 128K x16 bit Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. 0.0 0.1 0.2 History Initial Draft 0.1 Revision 0.2 Revision Remove BYTE option information Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns), tOE-55(30ns to 25ns), tWP-55(45ns to 40ns), tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns), ICC(2mA to 3mA), ICC1(2mA to 3mA) VIH level change from 2.0V to 2.2V Draft Date June 7, 2007 June 15, 2007 July 2, 2007 Remark 0.3 0.3 Revision Aug. 16, 2007 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Emerging Memory & Logic Solutions Inc. Zip Code : 690-719 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM620FV16B Series Low Power, 128Kx16 SRAM 128K x16 Bit Low Power and Low Voltage CMOS Static RAM FEATURES - Process Technology : 0.15m Full CMOS - Organization :128K x16 - Power Supply Voltage => EM620FV16B : 2.7~3.6V - Low Data Retention Voltage : 1.5V - Three state output and TTL Compatible - Packaged product designed for 45/55/70ns GENERAL PHYSICAL SPECIFICATIONS - Backside die surface of polished bare silicon - Typical Die Thickness = 725um +/-15um - Typical top-level metallization : => Metal (Ti/AlCu/TiN/ARC SiON/SiO2) : 5.2K Angstroms - Topside Passivation : => Passivation (HDP/pNIT/PIQ) : 5.4K Angstroms - Wafer diameter : 8 inch OPTIONS - C1/W1 : DC Probed Die/Wafer @ Hot Temp - C2/W2 : DC/AC Probed Die/Wafer @ Hot Temp 1 56 29 EM620FV16B (Dual C/S) + (0.0) EMLSI LOGO 28 y x Pre-charge Circuit PAD DESCRIPTIONS Name CS1,CS2 OE WE A0~A16 I/O0~I/O15 Function Chip select inputs Output Enable input Write Enable input Address Inputs Data Inputs/Outputs Name Vcc Vss UB LB NC Function Power Supply Ground Upper Byte (I/O8~15) Lower Byte (I/O0~7) No Connection A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VCC Row Select VSS Memory Array 1024 x 2048 I/O0 ~ I/O7 I/O8 ~ I/O15 Data Cont Data Cont I/O Circuit Column Select A10 A11 A12 A13 A14 A15 A16 WE OE UB LB CS1 CS2 Control Logic BONDING INSTRUCTIONS The 2M full CMOS SRAM die has total 56pads. Refer to the bond pad location and identification table for X, Y coordinates. EMLSI recommends using a bond wire on back side of die onto Vss bond pad for improved noise immunity. 2 EM620FV16B Series Low Power, 128Kx16 SRAM FUNCTIONAL SPECIFICATIONS There are 3 classifications for EMLSI die and wafers products, which are C1 and C2 for die and W1 and W2 for wafer, respectively. Each die and wafer support dedicated characteristics and probe the electrical parameters within their specifications. Followings are brief information for die and wafer classifications. Please refer to packaged specifications for more information but these parameters are not guaranteed at bare die and wafer. - C1 LEVEL DIE OR W1 LEVEL WAFER The DC parameters are measured by specification for C1 level die or W1 level wafer. The DC parameters measured at 70C temperature, which called `Hot DC Sorting' Other parameters are not guaranteed and warranted including device reliability. Please refer to qualification report for device reliability and package level datasheets for electrical parameters. - C2 LEVEL DIE OR W2 LEVEL WAFER The DC parameters and selected AC parameters are measured with for C2 level die or W2 level wafer. The DC characteristics of C2 die and W2 wafer is tested based on DC specifications of C1 level die and W1 level wafer. The DC and specified AC parameters are tested at 70C temperature, which called `Hot DC & Selective AC Sorting'. Other parameters are not guaranteed and warranted including device reliability. Please refer to qualification report for device reliability and package level datasheets for electrical parameters. C2 level die and W2 level wafer probe following AC parameter. - tRC, tAA, tCO - tWC, tCW PACKAGING Individual device will be packed in anti-static trays. - Chip Trays : A 2-inch square waffle style carrier for die with separate compartments for each die. Commonly referred to as a waffle pack, each tray has a cavity size selected for the device that allows for easy loading and unloading and prevents rotation. The tray itself is made of conductive material to reduce the danger of damage to the die from electrostatic discharge. The chip carriers will be labeled with the following information : - EMLSI wafer lot number - EMLSI part number - Quantity - Jar Packing : Jar packing is made by EMLSI and used by many customers that we deliver the requested die as wafer. The pack is consisted of clean paper to wrap the wafer, high cushioned sponge between wafers and hardly fragile plastic box with sponge. Each pack has typically 24 wafers and then several packs are put into larger box depending on amounts of wafers. Bond Pad #1 at Top Die orientation in chip carriers STORAGE AND HANDLING EMLSI recommends the die stored in a controlled environment with filtered nitrogen. The carrier must be opened at ESD safe environment when inspection and assembly. 3 EM620FV16B Series Low Power, 128Kx16 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature Symbol VIN, VOUT VCC PD TA Minimum -0.2 to 4.0V -0.2 to 4.0V 1.0 -40 to 85 Unit V V W o C * Stresses greater than those listed above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional oper- ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS1 H X X L L L L L L L L CS2 X L X H H H H H H H H OE X X X H H L L L X X X WE X X X H H H H H L L L LB X X H L X L H L L H L UB X X H X L H L L H L L I/O0-7 High-Z High-Z High-Z High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In I/O8-15 High-Z High-Z High-Z High-Z High-Z High-Z Data Out Data Out High-Z Data In Data In Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Stand by Stand by Active Active Active Active Active Active Active Active Note: X means don't care. (Must be low or high state) 4 EM620FV16B Series Low Power, 128Kx16 SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.23) Typ 3.3 0 - Max 3.6 0 VCC + 0.22) 0.6 Unit V V V V TA= -40 to 85oC, otherwise specified Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC ICC1 Average operating current ICC2 VOL VOH ISB VIN=VSS to VCC CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH VIO=VSS to VCC IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL Cycle time=1s, 100% duty, IIO=0mA, CS1<0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V, VIN<0.2V or VIN>VCC-0.2V Cycle time = Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL , VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CS1=VIH, CS2=VIL, Other inputs=VIH or VIL CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled) or 0V Min -1 -1 45ns 55ns 70ns 2.4 - Typ - Max 1 1 3 3 35 30 25 0.4 0.3 Unit uA uA mA mA mA Output low voltage Output high voltage Standby Current (TTL) V V mA Standby Current (CMOS) ISB1 LF - 11) 10 uA NOTES 1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested. 5 EM620FV16B Series Low Power, 128Kx16 SRAM VTM3) R12) AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL1) = 100pF + 1 TTL CL1) = 30pF + 1 TTL (only 45ns part) 1. Including scope and Jig capacitance 2. R1=3070 ohm, R2=3150 ohm 3. VTM=2.8V CL1) R22) READ CYCLE (Vcc =3.0 to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter Read cycle time Address access time Chip select to output Output enable to valid output UB, LB access time Chip select to low-Z output UB, LB enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB, LB disable to high-Z output Output disable to high-Z output Output hold from address change Symbol tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH 45ns Min 45 Max 45 45 25 45 10 5 5 0 0 0 10 20 15 15 10 10 5 0 0 0 10 Min 55 - 55ns Max 55 55 25 55 20 20 20 10 10 5 0 0 0 10 Min 70 - 70ns Max 70 70 35 70 25 25 25 - Unit ns ns ns ns ns ns ns ns ns ns ns ns WRITE CYCLE (Vcc =3.0 to 3.6V, Gnd = 0V, TA = -40oC to +85oC) Parameter Write cycle time Chip select to end of write Address setup time Address valid to end of write UB, LB valid to end of write Write pulse width Write recovery time Write to ouput high-Z Data to write time overlap Data hold from write time End write to output low-Z Symbol tWC tCW1, tCW2 tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 45ns Min 45 45 0 45 45 35 0 0 25 0 5 Max 15 55 45 0 45 45 40 0 0 25 0 5 55ns Min Max 20 Min 70 60 0 60 60 50 0 0 30 0 5 70ns Max 20 Unit ns ns ns ns ns ns ns ns ns - ns ns 6 EM620FV16B Series Low Power, 128Kx16 SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) tRC Address tAA CS1 CS2 tBA UB,LB tOE OE tOLZ Data Valid tOH tCO tHZ tBHZ tOHZ tWHZ Data Out High-Z tBLZ tLZ NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 7 EM620FV16B Series Low Power, 128Kx16 SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) tWC Address tCW(2) CS1 CS2 tWR(4) tAW tBW UB,LB tWP(1) WE tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tDH High-Z tOW TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED) tWC Address tAS(3) CS1 CS2 tCW(2) tWR(4) tAW tBW UB,LB tWP(1) WE tDW Data in Data Valid tDH Data out High-Z High-Z 8 EM620FV16B Series Low Power, 128Kx16 SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED) tWC Address tCW(2) CS1 tAS(3) CS2 tAW tWP(1) WE tDW Data in Data out High-Z Data Valid tWR(4) tDH High-Z TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED) tWC Address tCW(2) CS1 CS2 tWR(4) tAW tBW tAS(3) tWP(1) tDH UB,LB WE Data in Data out NOTES (WRITE CYCLE) tDW Data Valid High-Z High-Z 1. A write occurs during the overlap(tWP) of low CS1 a high CS2 and low WE. A write begins at the lastest transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition when CS1 goes high, CS2 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high. 9 EM620FV16B Series Low Power, 128Kx16 SRAM DATA RETENTION CHARACTERISTICS Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time NOTES Symbol VDR IDR tSDR tRDR Test Condition ISB1 Test Condition (Chip Disabled) 1) VCC=1.5V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form Min 1.5 0 tRC Typ2) 0.5 - Max 3.6 - Unit V A ns 1. See the ISB1 measurement condition of data sheet page 5. 2. Typical value is measured at TA=25oC and not 100% tested. DATA RETENTION WAVE FORM tSDR Vcc 3.0V Data Retention Mode tRDR 2.2V VDR CS1 GND Vcc 3.0V CS2 VDR 0.4V CS2 < 0.2V CS1 > Vcc-0.2V Data Retention Mode tSDR tRDR GND 10 EM620FV16B Series Low Power, 128Kx16 SRAM SRAM PART CODING SYSTEM EM X XX X X X XX X X - XX XX 1. EMLSI Memory 2. Product Type 3. Density 4. Function 5. Technology 6. Operating Voltage 1. Memory Component EM --------------------- Memory 2. Product Type 6 ------------------------ SRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 5. Technology F ------------------------- Full CMOS 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 11. Power 10. Speed 9. Package 8. Generation 7. Organization 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 8. Generation Blank ----------------- 1st generation A ----------------------- 2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation E ----------------------- 6th generation F ----------------------- 7th generation G ---------------------- 8th generation 9. Package Blank ---------------- KGD, 48&36FpBGA S ---------------------- 32sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 10. Speed 45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ---------------------45ns 55ns 70ns 85ns 100ns 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power(Pb-Free & Green) L ---------------------- Low Power S ---------------------- Standard Power 11 |
Price & Availability of EM610FR16AS-45LF
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |